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3D Imaging Analysis System
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Electronic Measuring Instruments
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Reaching New Heights of Speed and Accuracy
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System-on-a-Chip semiconductors (SoC devices) are experiencing boundless evolution for digital electrical appliances and mobile communications units. To make full use of SoC device capabilities, high-level quality tests are being performed. The T6683 SoC test system performs well for developing and evaluating SoC devices and for SoC mass production lines, because it measures at the highest-level speed in its class and with high accuracy.
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Adopts MULTi-pinTM Architecture
The T6683 adopts both the previous I/O-pin architecture and also ADVANTEST's MULTi-pin architecture with pins only for a comparator. Dead band avoidance ("Fly- By" connection), which becomes a problem with high-speed interface testing, can be performed without reducing tester channel resources.
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Significantly Improved Timing Accuracy
Based on the memory test system, with ADVANTEST's superior high accuracy timing generation technology, the T6683 achieves high timing accuracy, which is two times more accurate than former models. Additionally, by housing all circuits in a proven immersion cooling box, which is required for high accuracy, the T6683 is able to achieve thermal stability, and was able to be designed into a smaller enclosure.
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T6000 Series Uses Common Software
Since T6000 series of test systems adopt the Viewpoint software platform, individual software programs are highly compatible. Thereby, it has reduced the time required for developing test plan programs and their maintenance.
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| Major Specifications |
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| Target Devices: |
High-speed MPU, ASIC, SoC |
| Test Speed: |
250 MHz/500 MHz/1 GHz (data rate) |
| Number of pins: |
Up to 1024 I/O pins |
| Simultaneous testing: |
Up to 4 |
| Timing generation: |
6 timing edges/pin
256 timing sets (32 timing sets/pin) |
| Pattern generator (SQPG): |
64 MW pattern depth (standard) |
| Multiple DC test units: |
1 unit/16 pins |
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| Options |
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| SCPG: |
Operating frequency; 250 MHz
Memory capacity; 4 GW x 4 pins x 2 bits/pin or
1 GW x 4 pins x 2 bits/pin |
| ALPG: |
Operating frequency; 250 MHz
Address generation; 16X, 16Y
Data generation; 36D
AFM; 4 MW x 72 bits |
| HSCLK: |
4 Differential output channels at 1.2 GHz
(PLL output) |
| HCDPS: |
Up to 256 Amps (16 Amps x 16 channels) |
| AFG: |
Up to 4 output channels, 16 bits, 204.8 Ksps |
| AFD: |
Up to 4 input channels, 16 bits, 204.8 Ksps |
| VFG: |
Up to 2 output channels, 14 bits, 51.2 Msps |
| VFD: |
Up to 2 input channels, 12 bits, 41 Msps |
| SAMPLER: |
Up to 4 input channels, 1.5 GHz |
| SG: |
1 output channel, 1 MHz to 500 MHz |
| HRB: |
High-Speed Reload Buffer |
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